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CY7C1324F
2-Mb (128K x 18) Flow-Through Sync SRAM
Features
* 128K x 18 common I/O * 3.3V -5% and +10% core power supply (VDD) * 3.3V I/O supply (VDDQ) * Fast clock-to-output times -- 6.5 ns (133-MHz version) -- 7.5 ns (117-MHz version) * Provide high-performance 2-1-1-1 access rate * User-selectable burst counter supporting Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed write * Asynchronous output enable * Supports 3.3V I/O level * Offered in JEDEC-standard 100-pin TQFP package * "ZZ" Sleep Mode option Intel 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1324F allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1324F operates from a +3.3V core power supply while all outputs may operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Functional Description[1]
The CY7C1324F is a 131,072 x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is
Logic Block Diagram
A0,A1,A MODE ADV CLK ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC CLR Q0
ADSC ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER
BWB
MEMORY ARRAY
SENSE AMPS
OUTPUT BUFFERS
BWA BWE GW CE1 CE2 CE3 OE
DQA,DQPA WRITE REGISTER
DQA,DQPA WRITE DRIVER INPUT REGISTERS
DQs DQPA DQPB
ENABLE REGISTER
ZZ
SLEEP CONTROL
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05431 Rev. **
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3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised January 29, 2004
CY7C1324F
Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum Standby Current 6.5 225 40 117 MHz 7.5 220 40 Unit ns mA mA
Pin Configurations
100-Pin TQFP
BWB BWA CE3 CE1 NC NC VDD VSS OE ADSC ADSP ADV 86 85 84 83 CE2 CLK GW BWE
A
A 82
A
99
98
97
96
95
94
93
92
91
90
89
88
87
NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
BYTE B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
100
81
A
CY7C1324F
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50
A NC NC VDDQ VSS NC DQPB DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC BYTE A
38
39
40
41 VDD
42
VSS
NC NC A A
NC NC
A1
A0
43
MODE A
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NC
A
A
A
A A
A
A
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CY7C1324F
Pin Descriptions
Name A0, A1, A TQFP I/O Description 37,36,32, InputAddress Inputs used to select one of the 128K address locations. Sampled at 33,34,35, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 44,45,46, are sampled active. A[1:0] feed the 2-bit counter. 47,48,49,80, 81,82, 99,100 93,94, 88 InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes Synchronous to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge Synchronous of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous signal must be asserted LOW to conduct a Byte Write. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
BWA,BWB GW
BWE CLK CE1
87 89 98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE and CE to select/deselect the device. 1 2 InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronou I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O s pins are three-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it Synchronous automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH InputAddress Strobe from Controller, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a Asynchronou non-time-critical "sleep" condition with data integrity preserved. For normal s operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
CE2 CE3 OE
97 92 86
ADV ADSP
83 84
ADSC
85
ZZ
64
DQs
DQPA, DQPB VDD VSS
58,59,62,63, I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register 68,69,72, Synchronous that is triggered by the rising edge of CLK. As outputs, they deliver the data 73,8,9,12, contained in the memory location specified by the addresses presented during the 13,18,19,22, previous clock rise of the Read cycle. The direction of the pins is controlled by OE. 23 When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a three-state condition. 24,74 15,41, 65, 91 5,10,17,21, 26,40,55,60, 67,71,76, 90 Power Supply Ground Power supply inputs to the core of the device. Ground for the device.
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CY7C1324F
Pin Descriptions (continued)
Name VDDQ TQFP 4,11,20, 27,54,61, 70,77 31 I/O I/O Power Supply InputStatic Description Power supply for the I/O circuitry.
MODE
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die.
NC
1,2,3,6,714, 16,25,28,29, 30,38,39, 42,43,50,51, 52,53,56, 57,66,75,78, 79,95,96
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1324F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:B]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a Write) on the next clock rise, the appropriate data will be latched and written into the device. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are three-stated during a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:B]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are three-stated when a Write is detected, even a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1324F provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to an interleaved burst sequence.
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CY7C1324F
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
Truth Table[2, 3, 4, 5]
Cycle Description Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Snooze Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst ADDRESS Used CE1 CE3 CE2 None H X X None None None None None External External External L L L X X L L L X H X X X L L L L X L X X H H H ZZ L L L L L H L L L ADSP X L L H H X L L H ADSC L X X L L X X X L ADV X X X X X X X X X WE OE CLK X X X X X X X X L X X X X X X L H X DQ
L-H Three-State L-H Three-State L-H Three-State L-H Three-State L-H Three-State X Three-State
L-H Q L-H Three-State L-H D
Notes: 2. X = "Don't Care." H = Logic HIGH, L =Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BWA, BWB), BWE, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the Write cycle 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Three-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW)
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CY7C1324F
Truth Table[2, 3, 4, 5]
Cycle Description Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS Used CE1 CE3 CE2 External L L H External Next Next Next Next Next Next Current Current Current Current Current Current L X X H H X H X X H H X H L X X X X X X X X X X X X H X X X X X X X X X X X X ZZ L L L L L L L L L L L L L L ADSP H H H H X X H X H H X X H X ADSC L L H H H H H H H H H H H H ADV X X L L L L L L H H H H H H WE OE CLK H H H H H H L L H H H H L L L H L H L H X X L H L H X X L-H Q L-H Three-State L-H Q L-H Three-State L-H Q L-H Three-State L-H D L-H D L-H Q L-H Three-State L-H Q L-H Three-State L-H D L-H D DQ
Truth Table for Read/Write[2, 3]
Function Read Read Write Byte (A, DQPA) Write Byte (B, DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X
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CY7C1324F
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in Three-State ..................................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature] 0C to +70C -40C to +85C VDD 3.3V -5%/+10% VDDQ 3.3V -5% to VDD
Electrical Characteristics Over the Operating Range [6, 7]
CY7C1324F Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[6] Input Load Current (except ZZ and MODE) Input Current of MODE Input Current of ZZ IOZ IOS IDD ISB1 Output Leakage Current Output Short Circuit Current VDD Operating Supply Current Automatic CE Power-Down Current--TTL Inputs Automatic CE Power-Down Current--CMOS Inputs Automatic CE Power-Down Current--CMOS Inputs Automatic CE Power-Down Current--TTL Inputs VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 3.3V VDDQ = 3.3V GND VI VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDD, Output Disabled VDD = Max., VOUT = GND VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz -5 -5 30 5 -300 225 220 90 85 40 2.0 -0.3 -5 -30 5 Test Conditions Min. 3.135 3.135 2.4 0.4 VDD + 0.3V 0.8 5 Max. 3.6 3.6 Unit V V V V V V A A A A A A mA mA mA mA mA mA
ISB2
Max. VDD, Device Deselected, All speeds VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static 7.5-ns cycle, 133 MHz Max. VDD, Device Deselected, VIN VDDQ - 0.3V or VIN 0.3V, 8.0-ns cycle, 117 MHz f = fMAX, inputs switching Max. VDD, Device Deselected, VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static All speeds
ISB3
75 70 45
mA mA mA
ISB4
Notes: 6. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 7. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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CY7C1324F
Thermal Resistance[8]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 TQFP Package 41.83 9.99 Unit C/W C/W
Capacitance[8]
Parameter CIN CCLK CI/O Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V Max. 5 Unit pF
Clock Input Capacitance Input/Output Capacitance
5 5
pF pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 R = 317 VDD 5 pF GND R = 351 10% ALL INPUT PULSES 90% 90% 10% 1 ns
VL = 1.5V
1 ns
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
Switching Characteristics Over the Operating Range[9, 10]
133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Data Output Valid after CLK Rise Data Output Hold after CLK Rise Clock to Low-Z[12, 13, 14] Clock to High-Z[12, 13, 14] Low-Z[12, 13, 14] 0 3.5 OE LOW to Output Valid OE LOW to Output OE HIGH to Output High-Z[12, 13, 14] 2.0 0 3.5 3.5 0 3.5 6.5 2.0 0 3.5 3.5 7.5 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 8.5 3.0 3.0 ns ns ns Description VDD(Typical) to the First Access[11] Min. 1 Max. 1 117 MHz Min. Max. Unit ms
Notes: 8. Tested initially and after any design or process change that may affect these parameters. 9. Timing reference level is 1.5V when VDDQ = 3.3V. 10. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested.
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CY7C1324F
Switching Characteristics Over the Operating Range[9, 10]
133 MHz Parameter Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold after CLK Rise ADSP, ADSC Hold after CLK Rise GW,BWE, BW[A:B] Hold after CLK Rise ADV Hold after CLK Rise Data Input Hold after CLK Rise Chip Enable Hold after CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up before CLK Rise ADSP, ADSC Set-up before CLK Rise ADV Set-up before CLK Rise GW, BWE, BW[A:B] Set-up before CLK Rise Data Input Set-up before CLK Rise Chip Enable Set-up 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns ns ns ns ns ns Description Min. Max. 117 MHz Min. Max. Unit
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CY7C1324F
Timing Diagrams
Read Cycle Timing[15]
tCYC
CLK
t
CH
t CL
tADS
tADH
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
t WES t WEH
A2
GW, BWE,BW
[A:B] tCES t CEH
Deselect Cycle
CE
t ADVS t ADVH
ADV ADV suspends burst. OE
t OEV t CLZ t OEHZ t OELZ
tCDV tDOH t CHZ
Data Out (Q)
High-Z
Q(A1)
t CDV
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Single READ DON'T CARE
BURST READ UNDEFINED
Burst wraps around to its initial state
Note: 15. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
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CY7C1324F
Timing Diagrams (continued)
Write Cycle Timing[15, 16]
t CYC
CLK
t
CH
t
CL
tADS
tADH
ADSP
tADS tADH
ADSC extends burst.
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst.
A3
tWES tWEH
BWE, BW[A:B]
t t WES WEH
GW
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst.
OE
t t DS DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)
Data in (D)
High-Z
t OEHZ
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note: 16. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW...
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CY7C1324F
Timing Diagrams (continued)
Read/Write Timing[15, 17, 18]
tCYC
CLK
t CH tADS tADH
t CL
ADSP
ADSC
tAS tAH
ADDRESS
A1
A2
A3
t t WES WEH
A4
A5
A6
BWE, BW[A:B]
tCES tCEH
CE
ADV
OE
tDS tDH tOELZ
Data In (D) Data Out (Q)
High-Z
t OEHZ
D(A3)
tCDV
D(A5)
D(A6)
Q(A1)
Q(A2) Single WRITE DON'T CARE
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
Back-to-Back READs
BURST READ UNDEFINED
Notes: 17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed. 18. GW is HIGH.
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CY7C1324F
Timing Diagrams (continued)
ZZ Mode Timing[19, 20]
CLK
t ZZ t ZZREC
ZZ
t
ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Ordering Information
Speed (MHz) 133 117 Ordering Code CY7C1324F-133AC CY7C1324F-117AC CY7C1324F-117AI Package Name A101 A101 A101 Package Type 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack Industrial Operating Range Commercial
Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05431 Rev. **
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CY7C1324F
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
16.000.20 14.000.10
100 1 81 80
DIMENSIONS ARE IN MILLIMETERS.
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX.
0.10
R 0.08 MIN. 0.20 MAX.
0 MIN.
0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX.
SEATING PLANE
0-7 0.600.15
0.20 MIN. 1.00 REF.
DETAIL
A
51-85050-*A
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05431 Rev. **
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1324F
Document History Page
Document Title: CY7C1324F 2-Mb (128K x 18) Flow-Through Sync SRAM Document Number: 38-05431 REV. ** ECN NO. 200780 Issue Date See ECN Orig. of Change NJY New Data Sheet Description of Change
Document #: 38-05431 Rev. **
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